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What are Field Effect Transistor Used for

Warm hints: The word in this article is about 986 and  reading time is about 6 minutes. 
Guidance: We often come into contact with crystal three-stage transistors, and are familiar with their use. They are relatively unfamiliar to crystal field effect transistors. However, because of their unique advantages, such as high input impedance, low noise and good thermal stability, they are also common in our use. We know that there are many kinds of field effect transistors, which can be divided into junction field effect transistors and insulated gate field effect transistors according to their different structures. Insulated gate field effect transistors are also called metal oxide conductor field effect transistors, or MOS field effect transistors for short.

How to Prevent Breakdown of Insulated Gate FET

Because the input impedance of insulated gate FET is very high, this is its advantage, but it brings new problems in use. Because of the high input impedance, once the charged object is close to the gate, it is difficult to discharge the charges induced by the gate through the resistance. The accumulation of charges results in an increase in the voltage, especially when the capacitance between the electrodes is small, a small amount of charges will produce a higher voltage, so that the tube is not used. Or when welding, it has already broken down or the index drops down. Especially for MOS tube, its insulating layer is very thin and it is easier to break down and damage. In order to avoid such an accident, the key is to avoid the suspension of the grid, that is, the DC path must be maintained between the two poles of the grid source. Usually, a resistor (less than 100K) is connected between the two poles of the gate source to keep the accumulated charge from excessive, or a voltage regulator is connected to keep the voltage from exceeding a certain value. The three electrodes should be short-circuited and placed in the shielded metal box during storage; the electrodes should be short-circuited first when the pipe is welded to the circuit or taken off; the soldering iron instruments used in installation and testing should be well grounded, and it is better to unplug the power supply of the soldering iron before welding.

How to Judge the Electrode of JFET

Place the multimeter in RX1K block, contact the assumed gate G pin with a black pen, and then contact the other two pins with a red pen. If the resistance values are relatively small (about 5-10 Euros), then exchange the red and black pens and measure them again. If the resistance values are large (infinite), it means that they are all reverse resistance (PN junction reverse), belonging to the N channel tube, and the black meter. The tube contacted by the pen is gate G, and the original assumption is correct. The resistance values measured again are very small, indicating that the forward resistance belongs to the P-channel field effect transistor, and the black pen is also in contact with the gate G. If this does not happen, the red and black pen can be changed and tested according to the above method until the gate is judged. Generally, the source and drain poles of junction effect transistors are symmetrical in manufacture, so when the gate G is determined, it is not necessary to judge the source S and drain D, because the two poles can be used interchangeably, so it is not necessary to distinguish them. The resistance between source and drain is about several thousand ohms.

Estimation of amplification capability of field effect transistors

The amplification capability of FETs can be estimated by using the RX100 gear of the multimeter. Specific tests are as follows: red pen connects source S, black pen connects drain D, which is equivalent to adding 1.5 volt power supply voltage to FET, when the pin indicates the resistance between D-S poles. Then pinch the grid G with your finger and add the human body’s induced voltage to the grid as an input signal. Because of the amplification effect of FET, both Uds and Id will change, which is equivalent to the change of D-S interelectrode resistance. It can be observed that the needle oscillates considerably. If the hand-pinched grid gauge needle oscillates very little, it means that the amplification ability of FET is weak, and if the gauge needle does not move, it means that FET has been damaged.

Notice that the Rds of most FETs increase, the needle swings to the left, the Rds of a few FETs decrease, and the needle swings to the right. However, no matter the direction of the needle swing, as long as the needle can swing clearly, it shows that the tube has the ability to magnify. However, due to the higher input resistance of the MOS transistor and the acceptable inductive voltage of the gate, it is impossible to pinch the gate directly by hand. The insulating handle of the screwdriver must be grasped by hand and the gate must be touched by a metal rod in order to prevent the inductive charge from being directly added to the gate and causing the gate breakdown of the MOS transistor.

Examples (Summarizing the role of MOS gate resistance in analog circuits)

  1. Partial pressure
  2. Pull-down resistance is to discharge gate charge as soon as possible and cut off MOS transistor as soon as possible.
  3. Prevent grid surge and overvoltage (grid parallel regulators also prevent overvoltage)
  4. The full bridge gate resistance is the same mechanism. The gate charge can be released as soon as possible and the MOS transistor can be cut off as soon as possible. To avoid gate suspension, the suspended gate MOS transistor will turn on, resulting in short circuit of the whole bridge.
  5. The resistance between the drive tube and the gate acts as isolation and prevents parasitic oscillation. 报错

Relevant article:


20 thoughts on “What are Field Effect Transistor Used for

  1. Excellent~

  2. Very complete article, the whole chapter of knowledge is divided into several articles to write, and are continuous, convenient for readers to read, save time, but also very organized, thank the author.

  3. Hello~ sir
    Thank you for your excellent pages.

  4. Hello~ sir
    Thank you for your excellent pages, and I would like to ask a questions:
    FET is named Field Effect Transistor while field effect is also producing in bjt. What are the factors/reasons that FET is called field effect while bjt is not? I have read textbook but it didn’t explain it.

    1. An electric “field” is delivered at whatever point and any place there is a voltage distinction. In reality the field is in every case all over the place, yet moves toward becoming non-zero when voltage contrasts are non-zero. Since non-zero voltages are crucial to how every electrical gadget functions, every such gadget can be said to work dependent on or some way or another identified with the “field”.
      Field impact transistors (FETs) take a shot at a pricipal that uses the field delivered by the entryway such that makes the channel lead pretty much. In bipolar transistors, the present that can be conveyed between the gatherer and producer is balanced by the base current. Obviously there are electric fields inside a bipolar transistor. The FET was named such on the grounds that the of how the static field, as juxtaposed to current, assumes a focal job in the activity of the gadget.
      It’s a naming plan, which isn’t intended to be a nitty gritty portrayal of how the gadget functions.

    2. Well, I don’t know how to answer you questions…

  5. Sir, thank you for you contribution first.
    The regular nano-hardware are standing up to numerous bottlenecks and turn based gadgets have turned into the possibility for the cutting edge nano-hardware (spintronics).
    In the semiconductor channel, the Rashba impact will be utilized to get an appropriate turn precession point or stage move by turn circle coupling or entryway voltage.
    I need to realize that how to utilize the Rashba impact in the semiconductor channel to understand the on/off conditions of turn field impact transistor? What’re the jobs of turn circle coupling and door voltage?

    1. Thank you for you excellent question that let my post was more marvellous. About your problem:
      In the proposition of Datta and Das, turn enraptured electrons enter the FET channel through the FM1 contact. These turn enraptured electrons are not in a turn eigenstate of the two-dimensional electron gas. Along these lines the turn begins to precess in the turn circle attractive field natural for the material as the electrons spread. When the electrons arrive at the contrary contact FM2, they may be transmitted into this contact, if their subsequent turn lines up with the direction of the turn spellbound contact (low obstruction state). In the contrary case they will be reflected (high obstruction state).
      The job of the entryway voltage is to tune the electron thickness in the channel, and consequently the quality of the Rashba turn circle coupling, for example the quality of the inborn turn circle attractive field. Along these lines, the precession recurrence can be tuned, and, in principle, exchanging between the high and low obstruction states can be accomplished.
      Rashba turn circle coupling is identified with the structure reversal asymmetry of the divert toward the path typical to the channel plane. The entryway voltage can increment or abatement the vertical electric fields causing the structure reversal asymmetry. A nitty gritty depiction of this impact is nontrivial. It very well may be found in Roland Winkler’s book on turn circle coupling impacts in two-dimensional electron and gap frameworks. Tentatively it has been appeared, for instance, by Nitta and Koga that the quality of the turn circle coupling can be tuned in an InGaAs-FET structure. To date various different trials exist supporting this finding. An early survey of the field of spintronics can be found here. Various later surveys can be promptly found by a web search.

  6. I have to say that the author is very attentive in answering every question. I read the article and all the comments carefully, which really benefited me a lot.

    1. Thank you,ahlou G. !

  7. Good day, sir
    I’m an untrained specialist attempting to fix this engine driver circuit and was searching for some direction or help with investigating, or recreation. The circuit is from a handheld vacuum cleaner that quit working. I have send the specific situation to your email, could you give me some help?

    1. Hello~ manr
      Thank you for your trust, I have receive your email and reply it, you can have a check.

  8. I am writing the academic paper about field effect transistor, and this pages as well as other about FET in this website helps me a lot. Appreciate!

  9. sir, I am confusing about JFET, I always get confused about pinch-off voltage in junction field effect transistors, could you explain it?

    1. On the off chance that you know about BJTs, you control current from authority to producer (Ice) by changing the current into (NPN) or out of (PNP) the base (Ib). On the off chance that you deny the base of any current, Ice goes to zero. This is cutoff mode. So the BJT is a current controlled current source. The FET then again is a voltage controlled current source. In the FET you control the current from channel to source (Ids) by fluctuating the voltage at the entryway concerning the source (Vgs). For N-channel FETs, a positive-slewing Vgs yields a diminishing electric field in the channel (henceforth the name field impact transistor) and in this way an expansion in Ids, and alternately in the event that you drive the entryway voltage low enough WRT the source voltage, the electric field in the channel to-source channel broadens right over the channel to adequately square flow through the channel, so Ids goes to zero, and that Vgs is known as the pinchoff voltage. Same is valid for the P-channel FET with the exception of inverse extremity Vgs.
      You can reference to the page:

  10. Page give me a strong knowledge, i will be back in the fucture.

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