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Design of Data Recording System Based on Wireless Communication Technology

According to the special application requirements of an industrial field electronic device, this paper proposes a data recording system based on wireless communication technology.

Wide use of electronic recording devices

“Black Box” is one of the more popular electronic recording devices. It is widely used to record important data such as speed, direction, altitude, deflection angle, engine speed and temperature in real-time recording of aircraft, ships and automobiles. Through these data, you can understand the situation during its operation, and it is also an important basis for fault detection and analysis of the cause of the accident. In the industrial field, common recorders include pressure recorders, temperature recorders, humidity recorders, etc., for real-time monitoring of the production environment, thus ensuring efficient production and safe production.

There are usually two ways to download data from the recorder: download via a transmission cable and download it by plugging and unplugging the memory card. The former requires a cable to be connected, and the latter requires a memory card to be inserted and removed, both of which require structural disassembly. However, in some applications, the recorder is not easy to disassemble, especially in some radioactive industrial sites, and is not suitable for long-term close contact. In addition, these two methods may reduce the reliability of the system to some extent.

In this paper, based on the demand of data recording of an industrial field electronic device, a data recording device based on short-range wireless communication is proposed. The device downloads data in infrared or Bluetooth mode. Compared with the traditional data downloading method, the data is downloaded without the need to disassemble the device to connect cables or insert and remove the memory card, and reduce the contact that may be caused by the connection and insertion and removal of the memory card. malfunction.

Design requirements

During the operation of an industrial field electronic device, the recording system is required to record various electrical signals of the device and its working sequence in real time, for analysis of the operational status of the device after the event, as well as troubleshooting and positioning. The signals that need to be recorded in real time include 2 ARINC429 signals, 10 TTL digital signals, and 16 analog signals. The sampling frequency should be greater than or equal to 1 kHz and the recording time is about 1 h. Based on the number of signal channels, data acquisition rate, and data recording time, it can be estimated that the storage capacity of the recording system should be greater than 500 MB. Generally, the internal storage space of the microprocessor is limited, so the collected data needs to be stored in a non-volatile external memory. This system uses Sandisk’s 1 GB industrial grade CF card as the storage device.

System overall design

The system adopts the scheme of coordinated control of DSP and FPGA. The overall design scheme is shown in Figure 1. DSP mainly completes real-time data acquisition and control, FPGA data transmission, and data transmission with wireless communication module; FPGA implements data timing and logical timing control of CF card.

The DSP is the main controller. TI’s 16-bit fixed-point DSP chip TMS320F240 was selected. It has an instruction cycle of 50 ns, internal 544 words of RAM, 224K words of addressable memory, dual 10-bit A/D converters, 28 independently programmable multiplexed I/O pins, and 1 An asynchronous serial communication port (SCI) and a synchronous serial communication port (SPI). Its internal resources can meet the system’s requirements for TTL signal and analog signal acquisition. Through the external ARINC429, infrared and Bluetooth dedicated interface chip, ARINC429 data signal acquisition and two wireless modes of communication are realized.

The FPGA is an auxiliary controller whose core is a FIFO and logic control circuit for data transmission between the DSP and the CF card. The FPGA chip EP2C20Q240C8 of Altera’s CyclonelI series was selected. It has 142 user-available I/O pins, 52 M4K embedded array blocks, and 18,752 logic cells. The rich internal resources of DSP and FPGA meet the needs of system design.

The system mainly includes two functions: data storage and data download:

  • Data storage. The DSP realizes real-time acquisition of 2-way ARINC429 signal, 16-channel analog signal and 10-way digital signal, and stores the data in the FIFO of the FPGA in real time. When the FIFO stores a certain amount of data, the FPGA control logic automatically writes the data in the FIFO to the CF card.
  • Data download. First, the DSP sets the system’s Bluetooth and infrared modules as slaves. After receiving the connection request from the ground device with the Bluetooth or infrared interface held by the staff member, the authentication is performed first, and the connection is established after the authentication is passed. Then, the FPGA control logic circuit reads the data in the CF card and stores it in the FIFO, and the DSP sends the data in the FIFO to the ground device through the wireless communication module by querying or interrupting.

Functional module design

FPGA function module design – using FPGA to implement asynchronous FIFO module and CF card reading and writing module, is the focus of this design, but also difficult.

Asynchronous FIFO module–The data recording device has strong real-time performance and large data volume. In order to improve the data transmission speed and avoid data clogging, the FPGA hardware design flexibility is used to construct an asynchronous FIFO module with a width of 16 bits and a depth of 512 as a relay station for data transmission between the DSP and the CF card. The structure diagram of the asynchronous FIFO is shown in Figure 2. It includes four modules: a data storage module, a write address generation module, a read address generation module, and a flag generation module. The FIFO reads and writes using two clocks, the read clock and the write clock. The write clock synchronization signal has a write request and a write address generated by the write address generation module; the read clock synchronization signal has a read request and a read address generated by the read address generation module. Write enable and read enable are generated by DSP and FPGA data transfer control logic and cF card read and write control logic, respectively. The flag bit generation module generates a FIFO storage status flag from the read/write address relationship and feeds back to the host DSP. The DSP controls the data transmission with the FPGA by querying the flag.

CF card reading and writing module.–CF card reading and writing module is divided into CF card reading control module and CF card writing control module. The design of the CF card read or write module is similar. This only describes the working process of writing a CF card.

First, set the CF card’s property register. The CF card has four attribute registers. Usually, you only need to set the “Configuration Select Register” to select the CF card read/write mode. There are three types of CF card read/write modes: I/O mode, Memory mode, and True IDE mode. This design uses a 16-bit Memory mode to read and write CF cards. The Memory mode is the default read/write mode of the CF card, so there is no need to set the “Configuration Property Register” during CF card initialization.

Second, set the CF card’s task file register. The task file registers used in this design are: data register, sector number register, sector number register, low cylinder number register, high cylinder number register, drive select/head register, and status/command register. Set them, select the sector addressing mode, set the number of sectors read and written each time and the logical addressing address, and obtain the CF card status and input read and write commands.

The CF card is addressed in a similar way to the computer’s hard drive. There are two ways to address a sector: physical addressing (CHS) and logical addressing (LBA). This design uses LBA addressing and corresponds to a 28-bit LBA address. The head register stores 27 to 24 bits of the LBA address; the cylinder number register stores 23 to 8 bits of the LBA address; the sector number register stores 7 to 0 bits of the LBA address.

The process of writing a sector of a CF card is shown in Figure 3. Each time you store data to the CF card, you should first obtain the LBA address of the last stored sector to obtain the starting sector address of this storage. In order to record the address of the sector to be stored each time, a sector with an LBA address of 0 is reserved, dedicated to recording the sector address. Before starting a write operation, the sector with the LBA address of 0 should be read first to obtain the last stored LBA address; then 1 is added to obtain the LBA address of the write operation, and data is written to the specified sector.

Using QuartuslI as the FPGA development platform, the VHDL hardware description language is used to realize the interface between FPGA and DSP, the storage of asynchronous FIFO and the read and write logic of CF card. The simulation results of the write CF card timing obtained under the QuartuslI built-in simulation tool are shown in Fig. 4.

Wireless communication module design

Bluetooth module design

The Bluetooth module uses the BTM0604C2P. It is embedded with Bluetooth chip BlueCore4-Ext, compatible with Bluetooth 2.0+EDR specification, supports data rate of up to 3 Mbps, external antenna, effective distance of 10 m, and has standard UART interface.

The connection between the DSP and the Bluetooth module is established through the HCI protocol layer. The HCI (Host Controller Interface) protocol provides a command interface for the DSP to access the internal baseband controller and link manager of the Bluetooth module, and can obtain the configuration parameters of the Bluetooth chip.

In this design, the UART mode is used for communication between the DSP and the Bluetooth module. In addition to the asynchronous serial communication transceiver signals SCIRXD and SCITXD, the control signals used by the DSP have four control signals connected to the LNK, CLR, RTS and CTS pins of the Bluetooth module. The LNK pin is used to indicate whether the Bluetooth host and the slave connection are established, the ground device PC is a Bluetooth host, and the DSP is used as a Bluetooth slave; the CLR pin is used to switch the working mode of the Bluetooth module, including a parameter setting mode and a data transmission mode; The RTS and CTS pins are the “Request to Send” and “Clear to Send” pins, which are used to implement a dialogue between the DSP and the Bluetooth module to enable normal data transmission.

The SLEEP pin of the Bluetooth module can switch the Bluetooth module between sleep and wake-up status, and can also be used to clear the paired host address of the embedded chip memory of the Bluetooth module. The implementation of these functions is controlled by buttons, which distinguish the functions that need to be achieved by distinguishing the length of the buttons. The reset signal of the Bluetooth module is valid when a low-level pulse is input, and the pulse width is required to be greater than 5 mS.

Infrared module design

The infrared module uses HP’s infrared transceiver chip HSDL_1001 and infrared codec chip HSDL_7001, both of which follow the IrDA 1.0 protocol. The infrared signal is transmitted and received using the PWM scheme, and is modulated and demodulated by RZI coding. The modulation pulse width is 3/16 bits and the modulation frequency is 38 kHz. Due to the limitation of the hardware interface, the rate of infrared communication in the embedded system is 9 600 to 115 200 bps. The transmission of infrared data is based on the frame, and the 16-bit CRC code is used for data verification during transmission.

The system uses Maxim’s chip MAX3110 as the conversion chip between the SPI interface of the DSP and the UART interface of HSDL_7001. Both the MAX3110 and HSDL_7001 are powered by an external edgeless crystal oscillator circuit using crystals of 1.8432 MHz and 3.686 4 MHz, respectively. The data to be downloaded is first encoded by an infrared codec, and then transmitted to the PC in the form of an infrared light signal through an integrated light emitting diode on the infrared transceiver.

System software design

The functional timing flow of the system is shown in Figure 5. The DSP part program is written in C language, combined with hardware circuit to process and control data acquisition and data transmission. The main interrupt applications are ARINC429 signal acquisition interrupts and infrared communication request interrupts. The system’s workflow is based on the timing control process. After the system is initialized, task selection and execution are performed. If the specific I/O port is set to 1, enter the data storage program, collect the data and save it to the CF card; if the I/O port is set to 0, enter the data download program, wait for the connection request of the master device, authenticate and establish the corresponding Connect, read the CF card data, and send it to the master device through the wireless communication module.


The system utilizes DSP and FPGA cooperative control to realize data collection and storage, and uses infrared and Bluetooth modules to realize wireless download of data; using infrared and bluetooth instead of wired data and traditional data downloading methods such as plugging and unplugging memory cards, the operation is convenient and avoids A mechanical failure that can be caused by the traditional way. This recording system meets the data logging requirements of the industrial field electronics, enables real-time recording of the device’s electrical signals and control timing, sampling rates greater than 1 kHz, and the ability to continuously record approximately 1 GB of data. This design is an attempt to apply wireless communication technology to the industrial field electronic equipment. Relevant anti-interference and security issues need further research.


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